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Recent content by andy2000akimo

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    about low current LDO MPC1710 only 20na

    MCP1710 , not MPC MCP1710 Data Sheet - Microchip ww1.microchip.com/downloads/en/.../25158A.pdf‎翻譯這個網頁 provides high-current and low-output voltages, while maintaining an ultra-low 20 nA of quiescent current during device operation. In addition, the MCP1710 can.
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    [SOLVED] Model Library Files for Tanner EDA

    Sedit like cadence composer => need symbol , schematic library .. but many Fab only PDK .. some fab maybe have Laker UDD Tspice => just a spice tool , hspice , Tspice , dolphin smash , smartspice run spice model you need Fab provide process model file . Ledit => ledit can import GDS...
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    UMC 130nm Process doubt

    as I know , native nmos vt very low 0.5um normal VT=0.7 native nmos maybe 0.3v for 0.25um 0.18um maybe vt =0v for some mixer or amplifier need 0 VT but native mos is large area ..and someone siad have more noise couple ..
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    about low current LDO MPC1710 only 20na

    in standard cmos process . how to working in na current ? I ever try use mos current mirror when bias cureent less < 0.1ua some die have fail yield loss .. even simulation by hspice is ok , but real silicion have fail die how to design total 20na LDO ?? bandgap need current , OPA also...
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    spice model of depletion mode mosfet

    Re: depletion mode spice model GOOGLE Depletion Mode N-channel MOSFET .MODEL IXTT20N50D NMOS + LEVEL=3 + L=2.0000E-6 + W=5.5000 + KP=1.0446E-6 + RS=1.0000E-3 + RD=.22202 + VTO=-.89028 + RDS=20.000E6 + TOX=2.0000E-6 + CGSO=3.5684E-9 + CGDO=37.622E-12 + CBD=4.8729E-9 + MJ=1.5000 + PB=2.6055 +...
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    How to .ile skill file

    Hi : Which tools can de-compiler cadence use skill ile file to il code ?? thank you
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    is there cadence for window ?

    linux soft run fast than windows , Like hspice have Linux + win 32 .. windows OS performance about 70% linux in the same I7 3770K CPU ..
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    Power analysis using tanner tool

    goto china eetop forum , more ledit user and more ebook on site
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    REHL 4.5 can run on efi bios ??

    new CPU I7 + chipset also use efi bios , no legacy bios mode like asus motherboard .. and REHL 4.x or RHEL 5 can nor install on I7 .. how about eda tool in RHEL 6 ? IC610 , hspice , eldo also work fine on RHEL 6? or not thank you
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    who have benchmark hspice in Xeon VS K8

    find eetop have benchmark pll.sp .tran .tran 0.01u 從 2500u -> 25000us CPU clock OS sim-time ---------------------------- Intel Pentium4 3GHz RH8 1131s AMD opteron 2.8G RHEL4 676s AMD opteron252 2.6G RHEL4 727s Intel ex4400 2.4G centOS 4.5 508.2sec...
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    please help buck-boost with 4switchers inside design papers.

    TRY find out non-invert buck-boost Smooth Transition and Ripple Reduction in 4-Switch Non-Inverting A high efficiency, non-inverting, buck-boost DC-DC converter google can find some paper but non-invert buck boost have many patents when VIN close Vout and how reduce IL improve efficiency ..
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    s-edit schematic to l-edit layout

    Have anyone try sedit spice-in function ? Ledit 15.0 release new feature like spice_in maybe someday sedit can verilog-In ..
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    Recommend PDK for Tanner tools

    Re: pdk for tanner tools you can find MOSIS & chartered some ledit tdb file maybe someone also can provide other process tdb file
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    wich schematic tool is easy use on windows OS platform ??

    splan look like system level tool , like pspice orcad microsim .. microCap not like cadence composer ..
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    wich schematic tool is easy use on windows OS platform ??

    workview -> viewdraw -> dxdesigner I think it is good .. but cadence composer no windows base .. We can not read composer schematic on windows OS .. must be use vmware run linux OS ..

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