Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Anbusivam

  1. A

    How to simulate 45nm and 65nm together in Hspice.

    Hi all, I have a situation in which one of our 65nm chip is driven by one another 45nm chip. We are having some glitch problems at the interface and I need to debug the same to understand the glitch source. Now I've both the 45nm and 65nm process models and corresponding IO pad netlists. I am...
  2. A

    Help me understand a CDM ESD protection

    esd cdm protection circuits Hey ESDSolutions, Thanks for your reply. My doubt is it possible for the substrate to acquire +ve charge and how is that discharged during CDM event...?
  3. A

    Voltage and cell delay of a cell (STA)

    Hi, Can you tell me what is the additional corner added to take care Temp Inversion during the Design in 45nm. Thank for your time. Regards, Anbusivam
  4. A

    vcc vss esd protection circuit

    esd circuit for vcc Dear ESDSolutions. Very well explained. Thanks for helping me understand ggnmos better.
  5. A

    Explanation of the TLP testing method

    Re: TLP testing method Hello All, Can you please give me some waveforms on TLP testing. How is voltage levels up to 2Kv is acheived...? Regards, Anbu
See more

Part and Inventory Search

Back
Top