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Recent content by ananthan95

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    Artix 7 xc7a35t FPGA board

    yes. they have mentioned about XADC nothing specified about DAC as it is given for Spartan. I am confused... I couldn't find any short and precise article about the topic. they have different documentation for XADC. i am a beginner. i am having difficulty in understanding it. please help
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    Artix 7 xc7a35t FPGA board

    does Artix 7 xc7a35t FPGA board has onboard ADC and DAC like spartan 3e?
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    sending serial data with respect to a clock in a test bench

    for a better understanding, the above pic describes my question. S1 and S2 are generated inside the code. I should give the 16bit data (D) serially with respect to any of the signal. and this process should repeat 24 time because i have 24 data points of 16 bit each. after sending in the 24th...
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    sending serial data with respect to a clock in a test bench

    sorry. I guess my question wasn't clear enough. I actually want to avoid giving manual delays. this clk is generated inside the code. so I want my data to go in automatically with the clock (without me providing the delay manually). the Ton of clock is 620 ns and T off is 640 ns. so when the clk...
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    sending serial data with respect to a clock in a test bench

    process (clk) if falling_edge(clk) then adc <= '1';wait for 40ns; adc <= '0';wait for 40ns; adc <= '0';wait for 40ns; adc <= '1';wait for 40ns; adc <= '1';wait for 40ns; adc <= '1';wait for 40ns; adc <= '1';wait for 40ns; adc <= '0';wait for 40ns; adc <= '1';wait for 40ns; adc <=...
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    non responsive vhdl code in FPGA board

    no synthesis error and timing constraints are met. i ll upload the code below: in this code, the period of CLK is 20ns and demod_clk is 1320ns TX_DATA and RX_DATA are set of 24 data points which are...
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    non responsive vhdl code in FPGA board

    thank you for replying. but as I mentioned, it is working properly with a testbench. so I hope the code is ok. at least there is no error in the synthesis. and from the post-implementation time simulation, it gave a positive reply. it said the user timing constraints are met. and about the power...
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    non responsive vhdl code in FPGA board

    I wrote a VHDL code for synchronous demodulation. I use vivado 2016.4. it works perfectly with a testbench in the software. but when I burnt the code into the FPGA board (Xilinx Artix-35T FPGA (xc7a35ticsg324-1L)) it doesnt work. any suggestions? I used a software called terra term to read the...
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    reactive test benches

    I 'll post this as a separate thread. thank you for mentioning ILA. I have read more about it from the xilinx docs. now I am trying to add ila IP core to my design
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    reactive test benches

    thank you for responding. after the simulation, I implemented the design and ran a post-implementation timing simulation. it said all my timing constraints are met. and the tera term baud rate and fpga pin maping are checked. they are propper. even I have no idea how to add more details about my...
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    reactive test benches

    now I have a different issue. I wrote a VHDL code for synchronous demodulation. I use vivado 2016.4. it works perfectly with a testbench in the software. but when I burnt the code into the FPGA board (Xilinx Artix-35T FPGA (xc7a35ticsg324-1L)) it doesnt work. any suggestions? I used a software...
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    reactive test benches

    how do i do this? i couldnt find an example.
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    reactive test benches

    how to write test benches such that it will work like a feedback machine? I need the output of the VHDL programme as the next input in the testbench. if there is any link where I can read about it then that will be of great help.
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    creating an one time delay in vhdl test bench

    I am trying to write a VHDL test bench. the issue is, I have to write a code in such a way that a delay of 1000ns has to be executed in the beginning and later on the delay period is 620ns. so what should i do?
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    VHDL code for phase matching

    yea ok. so you think implementing such a code in VHDL is possible? because I have a bunch of integer data to process with.
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