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Hi all,
Could anyone comment (or share references) on simulating device variations in Cadence Spectre, particularly using the "VTA adder" methodology ? Thanks ~!
Hi all .. & a Happy 2018 New Year !
Does anyone know about the "VTA adder" methodology for Cadence Spectre simulations ? It is used to simulate the effect of process variations in CMOS analog circuits ? Could anyone describe it or share any references on this topic ? Thanks !
Greetings and a Happy 2018 New Year !!
Could anyone please shed some light on the "VTA adder" methodology for simulating the process variation dependence of analog CMOS circuits ? Also, are there any good references on this topic ? Thanks !
Greetings all ! :-)
I am trying to run sub-system level (a few blocks) mixed-signal ADMS simulation of an SoC. Here are some of the parameters:
'external' pwr supply, vdd: 5.5V
'internal' pwr supply, vcc : 1.8V
a2d, d2a defined for 1.8V domain
vdd is ramped. The only way I can get the...
Re: Apprentice question
Hi,
My opinion:
embrace could mean cover or address.
fit in its degenerate form means a certain size or footprint; i.e. 19" x 6"
form could mean a particular standard like vme bus or pcia etc
and
function would cover all the functional specs the circuit should meet...
Hi,
KCL is written at the two nodes in the model.
The first equation is for the total current flowing into 'node Vs', and the second is for the total current flowing out of the output node 'Vo'. It looks like a pretty good model because it includes noise currents (and noise voltages converted...
Hi all,
I am thinking of looking for a (hopefuly stable, long term) job in analog or "mixed signal" IC design. There is a plethora of job boards and job search engines and I was wondering if anyone could suggest which ones would be the best ones to use. I would prefer a site that is used by...
Hello all,
First of all, Thanks to whoever runs this forum...and thanks to the participants.
Am looking to start a venture in the field of design & validation of ICs. This would include consulting and applications development and can involve multinational operations (including China, of...
Hi,
I have an opportunity to take an 'intensive' introductory course in Perl :
'Perl Programming I' offered by the University of Calif., Santa Cruz Extension. This course is taught over three full days of instruction/lab by the author of the text :
'Perl by example, 4th ed.' by Ellie...
Re: how to increase the input impedance for a ring oscillato
Hi beabroad,
After looking at your schematic, it appears that when you measure Zin of the
ring oscillator, you are measuring the Zout of the diode connected FET, which
should be of the order of 1/gm. So, 100mohm is a reasonable...
Re: how to increase the input impedance for a ring oscillato
Hi beabroad,
Did you mean current starved? Because, if your current inverters are, in fact,
current saturated then how could you possibly change the inverter delay, and thus
the frequency, by any significant amount ?
Maybe that...
measure statements in spectre
Flamingo,
Thanks for the response.
I am using the command line interface to run spectre. I am not running it
within the Cadence Analog Design Environment. So to run spectre I give the
command
spectre filename.scs
Then I use the -format nutbin option to...
spectre measure
Hi All,
Greetings!
Can anyone help with measuring propagation delay in Spectre ?
In HSPICE, one can do the following, for instance:
.MEAS TPLH TRIG PAR('V(2)-0.5*VDD') VAL=0 FALL=1
+ TARG PAR('V(3)-0.5*VDD') VAL=0 RISE=1
How can we make the same...
spectre rmin
Vamsi,
Thanks for asking.
Actually, we have figured out what the problem is.
The problem is with the rpolyp.scs model file.
Altergroup excepts only model, instance and subcircuit statements,
which covers a lot of ground; however, there are statements in the
model file which are...
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