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Khouly,
Yes I tried with both the options (with and without initial condition).Also, I am using VDD as a step (with a rise time of 1n and transition from 0 to 3.3V).
My doubt is, will this be a problem with PMOS load (say load is less than expected)..... I have done the individual delay cells...
Hi,
I am presently designing a differential delay cell VCO which is based on symmetrical load and replica bias. (Its a 5 stage VCO)
O/P of the amplifier is used as a bias for PMOS load and Control voltage from LPF is used to control the tail current of delay cells. (Single NMOS as a tail...
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