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Recent content by analogdesk

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    Standard Cell Dynamic Power Calculation in SPECTRE ?

    Hello, Did you get help on your issue because I am facing the same problem? No outcome from Cadence support yet. I am trying to recover .lib data with spectre simulations both for delays/transitions and power. I have tried different formula for power (avg, rms, ...) but It is far away to match...
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    Job opportunity / partnership

    Hi, I am located in Grenoble, Fr. and looking for a Sr analog/mixed IC design engineer position Telecommuting (or Freelance) and frequent travel is possible if outside of Grenoble area. EDA tools availability can be figured out. - 15 years strong experience in CMOS/BiCMOS IC design: PLLs...
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    Sr Analog/Mixed IC design eng. looking for job opportunity

    Hi, I am located in Europe and looking for an analog/mixed IC design engineer position - Telecommuting or Freelance - Frequent travel is possible. EDA tools availability can be figured out. - 15 years strong experience in CMOS/BiCMOS IC design: PLLs, DLL, ADC/DAC, voltage regulators, AGC and...
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    Cadence Monte Carlo Mismatch simulation - Correlation

    Hope this helps... https://www.designers-guide.org/Modeling/montecarlo.pdf Rgds,
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    CMOS Image Sensor continuous time readout

    Hello, Can anyone explain the continuous time column parallel readout mentioned in this ST paper. I know Sony does the same too. How does this work ? Usually, there are sampling capacitors for reset and signal pixel levels. Thanks,
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    Why we use by-pass caps in layout?

    Re: By pass caps To filter out high frequency noise as close as possible from your circuit.
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    Can anybody check this issue for icfb?

    Yes, Cadence is very picky...It kept your vpulse in memory somewhere. You need to erase V3 and re-instantiate your vpwl. Regards.
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