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Hi,
Since amp pole is dominant, can an ac coupled local feedback loop help?
---------- Post added at 09:22 ---------- Previous post was at 07:52 ----------
Hi alterlinks,
Is the cap (connected in red) to move the second pole? If so, that wouldnt alter the location of amp pole, so no change...
Re: Razavi Bandgap for 5V Vdd
Hi,
The op-amp for fig 11.3 shld be 2-stage, with high current sinking capability in the second stage. But single stage is enuf, for sec 11.39.
Hi,
First of all, gm effcieny is at the max in subthreshold when compared to saturation. If you are suggesting that it will respond slowly due to the parasitic cap due to the large device, then it shld be the same case as in saturation too.
Hi gold,
I guess the feedbcak is proper.
Hi lovaraju.ch
I guess you have made the dominant pole at the o/p of the OTA. In that case, when the o/p current decreases, the output pole moves towards the dominant pole, reduction in Phase margin. But I didnt understand how subthreshold region...
Due to 12uF cap, the pole will occur very well at a lower frequency, there by giving a 90 degree phase shift to the Postive feedback, given by Q1, Q2, M1 & M2. So, this phase shifted +ve loop & the original negative feedback, given by the source degenearation resistance combinedley can have 2...
Hi,
I agree. But isnt it, due to the cap added, the frequency dependent phase shift will occur at a lower frequency, there by inverting the characteristics of the +ve loop. So, before UGB, we can get 2 possible -ve feedback. And increasing R1 will results in increasing the negative f/b...
Hi varun,
I agree, M4 always follow M3. But when vin2 increses by more than 2-3 overdrive voltages(after which it enters linear region), almost all the current will flow through M2. But until then it should be a linear increse in current. Correct me if I'm wrong.
Hi,
In linear region, Id is very much dependent on Vds. So, even a small variation in vds(lets assume comes from poor mismatch), can change the curr a lot, which needs to be avoided.
Hi iVenky,
I guess you are talking abt the closed loop transfer function. If so, then you have 2 poles, but one is LHP & the other is RHP. So, as such you cannot find any information from mag plot (eventhough there would be 40dB rolloff), but I guess the phase plot would be weird, ie, kind of...
Hi lei6042,
I assume you are using famous form of LDO. Then generally you will be placing output pole to be dominant compared to the input pole(Amp pole), which generally improves the PSRR of the LDO. So, in your case, you have to place your output pole atleast at 48MHz to get a good PSR for...
If I have understood it correctly, you are suggesting to use skewed kind of buffer. But, my problem is DC level shift doesn't happen always, which in a way avoids us from using skewed buffer.
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