Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
If i bias a transistor in linear range (in cascode current mirror) i.e., vgs>vth & vds < Vds,sat; then how to increase vds?
In a current mirror, Ibias decides Vgs.
As per long channel current equation, if we change (W/L), vds,sat changes. But how to change vds?
vdsat mosfet
If Vdsat is very low say around 50mv, we cann't assure the proper operation of mosfet in saturation after fabrication (because of weak inversion)
And also it depends on speed/power applicaion.
If it is for speed, vdsat should be more and if u want high gain, it should be less.
supply undervoltage design
How can i include hysteresis?
Is it sufficient to introduce hysteresis in comparator? or i have to introduce it externally?
If externally, how to include it?
i too don't know and sometimes a little bit confusion too,
why an application engineer paid so high, still yet people want to be in design field?
what's the difference work wise?
please anybody clarifies...
In unity gain feedback toplology plot the input and output and the current through the diff amp
the input voltage till which the output follows, gives you the input common mode range
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
