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Recent content by analog_member

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    how to design a dual-modulus divider in ADS 2009?

    that is what I'm doing, I'm replacing the VCO divide-by-N block present in ADS by my VCO, but i need to design a dual-modulus divider to divide the VCO frequency, as a fractional-N frequency synthesizer requires a frequency divider after the VCO.
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    how to design a dual-modulus divider in ADS 2009?

    Hi all!! I'm designing a fractional-N frequency synthesizer in ADS. I have designed the VCO , and i want to design a dual-modulus divider for dividing the VCO's output. I do not want to use the already available VCO divide-by-N block present in ADS as then i cant make use of my designed VCO...
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    help in xilinx system generator

    ya i did check its functionality first with only the simulink blocks , it worked fine. I'm buidling a mixed signal feedback system, hence the digital blocks i have replaced with the system generator blocks with proper gatewayin and gateway out blocks. But i cant replace the analog blocks for...
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    Dual modulus prescaler

    Hi Don P John, I'm also searching for dual modulus divider design either in VHDL or matlab. If u know do help me.
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    calculate phase margin of PLL

    U can use the function "bode(c)" to plot the bode diagram and then use the function "margin(c)" to give the phase margin, where c is the pll /system.
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    help in xilinx system generator

    thank u mano1998. I do know we should only put xilinx blocks within gatewayin and gateway out. I did the same, i have used xilinx adders and multipiers to build a filter ( keeping them inside the gateway in and gateway out ) and connected them to simulink analog filter and continuous vco block...
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    help in xilinx system generator

    i would like to know if we can build a feedback system using the xilinx system generator blocks. some blocks are the xilinx blocks some are the analog filter and vco of the simulink blocks. Its not working for as the input the vco is always at zero , hence the vco output frequency does not...

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