Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by analog_malware

  1. A

    VCS in EDA playground, not detecting module defined in another file

    Hi, My top module instantiates a module defined in another file with some parameters. The files are SystemVerilog, and the code synthesizes and simulates as expected in Vivado. In EDA Playground, for some reason, I am getting an error every time the top module tries to instantiate the lower...
  2. A

    Good practices to handle Empty/Null values in RTL

    Thanks a lot for the tips! I have added a new port to accept the number of integers, and an internal signal to keep track of the first empty position. I cannot use FIFO because my logic requires going back and forth across the array.
  3. A

    Good practices to handle Empty/Null values in RTL

    Hi, I am designing a module, which operates on an array of integers. The module is designed for a maximum array size of 16 integers, however, it can be less than 16 as well. I was thinking that when an array of size lesser than 16 is fed to the module, the rest of the positions would assume...
See more

Part and Inventory Search

Back
Top