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ricklin
thanks,i learn this method from papers,for example,1GSPS digital output code is decimated by 16, which means 64MSPS digital output code rate. low speed digital code is analy by logic analyzer,then we can get dynamic parameters (SNR SFDR) through FFT analy.I confuse how we carry parallel...
i will design >1GSPS flash adc,but i do not konw how to convert 2GSPS digital code low speed digital code which logic analyzer can sample up to 500MHz.
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