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Thanks dave for input. this is new information that i knew we can use iff inside a @ event.
The same code provides different output when run on questa simulator: (The original code i posted)
# [ 15]:: After waiting for cb.data
# [ 25]:: After waiting for cb
We are using clocking blocks in systemverilog. we are seeing some weird behaviour when we are waiting on clocking block input signal
We wait for the input of clocking block signal to change to '1', then wait for one clock and then read some signal. But when we wait for one clocking block, one...
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