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Agree with you, Sutapanaki. Especially when working in lower technology nodes like finfet and all, it's not correct to assume gamma of 1. I was just trying to see if I am missing anything else.
Sutapanaki, I guess you are talking about the excess noise from gamma factor of the MOS that changes the integrated noise from kT/C to kT/Cm * gamma. If you assume gamma = 1, you should always see kT/C noise as the output integrated noise of any S/H circuit. It is the source of noise and the...
You should be able to match the simulated noise number exactly to the kT/c value. Different sample and hold circuits will not have different noise unless you have more than one sampling operation taking place.
I agree with guntherleet. You should not do acnoise on a circuit that is not time invariant.
Sample and hold falls into the category of what is called Linear Periodically Time Varying (LPTV) circuits, whose steady state depends on the switching frequency. Go through the literature to get more...
While more detail always helps to get the best of the members here, I would suggest you to go through IEEE papers. You should be able to get enough information on LNA matching as it is a well known and most common problem one would encounter.
There used to be an option (at least in Calibre) to extract the parasitic with appropriate temp coefficients. In that case, depending on the simulation temperature, the parasitic value will be calculated during netlisting and this way, a single extraction would suffice. There must a similar...
Stacked device will not come in the technology library, neither can you configure it by changing any settings. You will have to manually stack the devices, which is like a cascode device with gate tied to the main device. This will almost behave like 2x length device for output impedance, but...
Mostly in technologies below 28nm, pmos and nmos are of similar strength. In that case, you can go with equal sizes for both. You can determine the inverter trip point either in DC or transient sim if you are interested. Based on that you can size pmos/nmos ratio to hit a precise vdd/2 trip...
Yes, that should give a very good idea of to what accuracy you will be able to measure the temperature. The thing to ensure is that with the sinusoid input, the harmonic distortions are well below the quantization noise floor which means that your temp accuracy is only limited by the ADC SQNR.
For characterizing the circuit, you can assume that the input (temp) is varying slowly (indeed the temperature will be varying). You can use very slow sinusoid to characterize, say 100Hz or so.
Just do the STB analysis manually. I.e break the loop manually ensuring DC operating point is not affected. Consider the loading at the location of breaking. Now check with and without bondwire the difference. Also, another cleanest solution is to not break any loop, but look at the step...
FFE resembles an FIR filter.. and the FFE is used in serdes transmitter output stage for partially compensating for channel loss, and in serdes receiver for equalisation.. so he is asking about FIR in context of serdes.
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