Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
orcad worst case
Hi,
I'm using Orcad 15.7 and when using the capture cis with Pspice A/D ( not Pspice A/D basic) to make worst case analysis, this option is not active !!!!. i don't know why? and (save bias piont and the other options are not active ?
Does anyone know why ??????????????????
for ise, the only way to map the package pins to vhdl ports is ucf. the ucf contains many constraints i think u need just "the pin assignment constraints". simply select the top level file of ur project, go to the processes window, expand the tree of "user constraints" and double click on...
Hi,
Can anyone tell me How i can create The Footprint in Orcad for FPGA Spartan 3E FG320.
I have the Pinout tables in EXCEL format but i don't know how can i create the footprint from it.
Thanks guys.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.