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Recent content by ★jerome&#97

  1. &

    Devide frequency into 3 using AHDL or Verilog HDL

    why not to decompression the file-Ndiv_v1.zip.
  2. &

    DSP core in FPGA, is it possible?

    i think u must't make a dsp core.Dsp is intent to digital signal processing, so you can do that wiht fpga, for example ,FFT, FIR or other arithmetic.
  3. &

    Can I use Protel software to simulate digital IF receiver?

    Re: Digital IF Receiver it's a challege to do that about high sample. yout must read the specification.
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