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except switch capacitor and mos in triode (too large leakage)
do you kind to tell me the way to achieve a large resistor (>1G) in cmos process?
thank you very muchi
Re: adc noise
it's my method. as it's hard to simulate the noise of swith capacitance circuit, so maybe you can simulate sampling and integrating period seperate, and calculte the whole result by hand.
Re: Maybe silly question about first-order sigma-delta modul
i think CT sigma delta must be quite different from DT ones, except the GBW, may the feedback time of quantizer should be considered.
Re: capacitor mismatch
i think you can read the technology file from foundry
uote="rampat"]how to calculate capacitor mismatch number from spectre model ?
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