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Thanks a lot for your kind reply, it worked...
I also found that another command, "hspice <filename>.sp > <filename>.lis" can also be used to generate .lis file.
Just an additional thing, I would like to know that in the lis file details, the "Total CPU time" is shown as 0.00s (probably it is...
Hi
When I simulate the .sp file using HSPICE, I get .ic0, .st0, and .tr0 files as a result after the simulation.
May I know, why I am not getting the .lis file in addition to the above other mentioned files?
Thanks
Amit
Hi there,
The technology node defines the device channel length. The transistor fabricated in an IC on a wafer acts as a unit block for the entire IC. The billions of such transistors fabricated on the IC completes the Front End of Line (FEOL) part.
The Back End of Line (BEOL) consists of...
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