Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by Amir.B

  1. A

    How to generate a look-up table from MATLAB on FPGA in Verilog?

    No, No, Never... Your guide was so useful for me, I say this seriously... :) thanks, once again!
  2. A

    How to generate a look-up table from MATLAB on FPGA in Verilog?

    Thank you so much dear kirill, for your kind consideration...
  3. A

    How to generate a look-up table from MATLAB on FPGA in Verilog?

    hi dear all... I have a vector consist of sine and cosine valus (A complex exponential) in MATLAB. How to generate a look-up table with this values in verilog? I know that should be use a block-RAM, but I don't know how to write verilog code. please help me. the values placed in a 4096×1 vector...

Part and Inventory Search

Back
Top