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Recent content by Aminos

  1. A

    Error generated by Design_analyzer from synopsys (DDX-2)

    unfortunatly no, cause we re supposed to work just on this ynthesizers, do you have any other idea to avoid this problem?
  2. A

    Error generated by Design_analyzer from synopsys (DDX-2)

    yes i know that but this signal is an instanciation of component: half_multiplier:multiplier port map( a => b (5 downto 0), . . . );
  3. A

    Error generated by Design_analyzer from synopsys (DDX-2)

    the ports are diffrent sizes but i m using just the bits that i need: example suppose that a : std_logic_vectot (5 downto 0) an b : std_logic_vector (10 downto 0), i put in my vhdl code: a => b(5 downto 0), the functional simulation (Modelsim) before the synthezis works correctly, the pbl is...
  4. A

    Error generated by Design_analyzer from synopsys (DDX-2)

    i was trying to synthesize my project using design_analyzer and analyzing step works correctly, but the elaborating steps generates this message: "ERROR: in design 'multiplier', connectionto port 'a' of instance 'half_multiplier_0' is too narrow. (DDX-2) can anyone help me please to resolve...
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