Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
hi arjun,
the worst condition or highest IR drop will be in BEST condition because the cells will be switching faster (rise-fall times lesser) and hence during clock rise-fall times, more flops & last stage clock buffers will contribute to peak current and you will see more IR drop
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.