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i didnt get wat u said..which attachment and where to see it...
---------- Post added at 11:20 ---------- Previous post was at 10:58 ----------
is ther any site for tat..
ya...with synchronous reset and synchronous hold..
---------- Post added at 09:13 ---------- Previous post was at 08:48 ----------
module(clk,hold,reset,q);
input clk,hold,reset;
output [15:0]q;
reg [15:0]q;
initial q=15'b0000000000000000;
always @(posedge clk)
begin
if (reset)...
i need a verilog code for phase detector to detect a positive edge of two clocks i.e one fast clock signal and one slow clock signal, simultaneously and produce output as just a single pulse..i need it soon..pls help out.
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