Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by amar.reddy4020

  1. A

    DFT with LSSD cells - S1-error after when i run post-DFT drc

    Re: DFT with LSSD cells S1: is scan chain blockage after (cell number is scan chain ) cells. I'm using dc to do this and my protocol is perfect. I hope there is problem with LSSD State table in the Library.
  2. A

    DFT with LSSD cells - S1-error after when i run post-DFT drc

    dft lssd Hi friends, I got the S1-error after when i run post-DFT drc. I wrote out my net list then i found that my SN pin of latch which is connected to permanent-1 in functional mode is now connected to SCLK (Scan Slave Clock). Can anyone help me in debugging this. The scan type is LSSD...
  3. A

    Question about DFT scan chain

    dft question on problmes Hi friends, I got the S1-error after when i run post-DFT drc. I wrote out my net list then i found that my SN pin of latch which is connected to permanent-1 in functional mode is now connected to SCLK (Scan Slave Clock). Can anyone help me in debugging this...

Part and Inventory Search

Back
Top