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Recent content by always@smart

  1. always@smart

    3- or 4-wire dc motor driver design

    noone done this kind of project before?
  2. always@smart

    3- or 4-wire dc motor driver design

    dear all, anyone of you have designed 3- or 4-wire dc motor driver b4? i wonder how you model the motor with TACh output and PWM input? any spice model? Thanks and regards, smart
  3. always@smart

    how to design a robust current mirror?

    dear evilguy, can you pls upload the paper. thanks in advance.
  4. always@smart

    Can I use two switches to realize four states?

    Re: help! 2 switches can be decoded to 4 cases, each case turn on each gain u need. hope this help
  5. always@smart

    how to do the stb analysis for opamp in cadence virtuso

    op amp tutorial with graphs 1. put a "iprobe" in where u break the loop. 2. in "stb" analysis, choose that "iprobe" as ur instance hope this helps
  6. always@smart

    PSRR Measurement of Voltage Regulator

    hi anachip, if you r using spectre, you can use the XF analysis, it allow you to small signal analysis from different input sources which with respect to your output. After run, go to direct plot, and check the XF result. hope this help
  7. always@smart

    problem on using cadence stability(stb) analysis

    cadence stb For multi-loop stability analysis, you should check the inner loop first and the outer loop check later. so in your case you should make sure the CMFB has enough of phase margin, then proceed to the RC feedback path. Hope this helps Regards, Smart
  8. always@smart

    What's the operating Points regions stand for? (in Spectre)

    Re: What's the operating Points regions stand for? (in Spect --------------------------------------------------------------------------------------------- HI , In spectre, the operating region is : 0 -> Cut-off 1 -> Linear 2 -> Saturation 3 -> Weak inverstion 4 -> Break down hope this help...
  9. always@smart

    Vth variation of PMOS transistors

    Re: corners Jutek, To me, the output variation is normal (with the corner), the overall variation in waveform shows only about 10mV (0.798~ 0.808v) across the process. You may check if all the MOS in your design is in satuation or not? How much the loop gain variation across corner...
  10. always@smart

    Vth variation of PMOS transistors

    Re: corners Hi Jutek, Pls label the signal. One thing i can see from the waveform is that the phase margin is not well compensated yet. Another thing is : why you call it corner? corner supposed to be simulated accoss all the PVT. or you meant something else? regards, smart
  11. always@smart

    Vth variation of PMOS transistors

    Re: corners hi jutek, ok, let's stick with the case when vdd=1.3v. so in this case the vout = 0.8v, RL=8, so the driving current is 100mA,right? I think it just make sense to me, it need such a big size to current for so much current. Otherwise, if you decrease the size, the pass transistor...
  12. always@smart

    Vth variation of PMOS transistors

    Re: corners Hi Jutek, the process compesation technique is application depandent. For an simple example: A voltage regulator which can regulate the stable output voltage at all corner. you can probably post your circuit, without knowing it, it's hard help you. regards, smart
  13. always@smart

    Vth variation of PMOS transistors

    Re: corners I think it's possible. just for your reference: the IBM 0.18um that i'm currently, PMOS's vth variation is about 200mv. you may use feedback circuit to compensate the process variation. regards, smart
  14. always@smart

    Why does the ac curve of this OPA has no -3dB breakoff point

    Re: Why does the ac curve of this OPA has no -3dB breakoff p Dear huojinsi, I have few comments here: 1. Are you sure your MOS size is correct? should it in micro meter range? please check and confirm with us 2. Can you please change your Capacitor value C1=1GF and instead of putting the...

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