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Re: LDO internal zero
I have seen this paper before.the goal of this circuit is to increase the effective cap of C1(in the picture),the theory of the zero introduce is just as byellow said:"connect a resistor to the bypass capacitor ". in fact, you can push the pole to 5MHZ just as the author...
The random offset voltage of the input composed of delta(Vth)、delta(W&L) and delta(ID),but how to caculate the influnence of the delta(ID)?when M3&M4 are replaced by resistors,then we can get delta(ID) by delta(R).in the case of mos transistors, how to caculate?Is it right to assume...
Re: LDO's PSRR
The LDO's PSRR is just the loop gain of your LDO.If only CMOS technology available, because there always exists a low pole at the output, So I think the way to do such a high GBW LDO, you must increase the low frequency gains.You can see papers of HUST of P.K mok's student. they...
Re: How to get charge pump voltage doubler's switch bulk vol
thanks you two, there remain two questions:
1) In my circuit, S1 S3 S4 are all PMOS switchs.My new question maybe how to determine the source of S3&S4, I have seen a paper that S3's source is connected to A,S4's source is just...
Just as described in the pic:
My question is how to determine the bulk(S3,S4) voltage?
I want to get a regulated voltage vout:vin<vout<2*vin,so there maybe 3 different
voltage levels:vin,vout,v(A);to prevent leakage current,the bulk (S3,S4) must be connected to the highest voltage, I have...
Just as described in the pic:
My question is how to determine the bulk(S3,S4) voltage?
I want to get a regulated voltage vout:vin<vout<2*vin,so there maybe 3 different
voltage levels:vin,vout,v(A);to prevent leakage current,the bulk (S3,S4) must be connected to the highest voltage, I have done...
I think the problem is not the 10v output voltage ,but the 1mA load current with so small caps.To supply such a large current, the switch frequency must be quite high,maybe 10meg,the efficency can't be high.Just guess/
I think : "the gain from the gate of M1(2) to OUT is 1 " is under the condition that the size of the mirror pairs is the same,and the RL is much larger than 1/gm. -Gm6*(r03||r06) is just the gain of the first stage.i believe the second stage gain=...
Hello sankudey: It 's right that the delta-Vab will determine the propagation delay ,but how can we test the minimun propagation delay and maxium one?If we test the min p-delay,if the difference between Va and Vb is small enough,the time will be very long, so how to determine the delta-Vab when...
I see.thanks every one
Added after 10 minutes:
Do you mean: when SNR is good ,then the INL is good.just like sunking's curve,the vout will come near to the ideal curve. that's the better the SNR,the vout will more like the ideal vout.
what do you mean "because of the process model"?
Let's assume vth=1v(tt) vth=0.9v(ff) then
when vin=1.1v Vgs-Vth=0.1(tt) 0.2(ff);
but when vin=3.3v Vgs-Vth=2.3(tt) 2.2(ff);
so you can see why when vin is low the change ratio is large.
Re: Question about LDO
the cap is to provide a low freq pole to filter the noise,and reduce the time for stablizing output.
but can anybody explain: with the low freq introduced , How to maintain stable?when we dc AC simulaition,we always inject AC signal from the vref point,and see the AC...
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