Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I need a model of a vertical transistor (BSIM-CMG) for modeling in LTspice. Unfortunately, the transistor model was in verilog. So I created a .sp file to transfer the model to hspice. However, when running the transistor model, LTSpice writes an error about the unknown variable nmos1. In this...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
