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Recent content by AlinParcalab

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    Pipelining 32 Bit Multiplier in Verilog

    I have rewritten everything, but the total delay on 32 B I think will really big. About the coding style, if could you give me some hints, and about that FSM since you have spoken about it I have a question, how could I pipeline the FSM I am thinking about it since a while already because a...
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    Pipelining 32 Bit Multiplier in Verilog

    I understand, at the moment I do not have acces to Cadence tool, the target was to buy them afther I have design which works and have a working RTL. But let's say and warning like this "Unused sequential element St2_Ac_reg was removed." from my point of view is clearly not good since if I look...
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    Pipelining 32 Bit Multiplier in Verilog

    My bad, my point was, how can I fix these warrning, why are they there? - - - Updated - - - My bad, my point was, how can I fix these warnings, why are they there? Is is because synthesis too is an FPGA tool, will it compile and work just fine with Cadence synthesis tool for Asics? I am...
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    Pipelining 32 Bit Multiplier in Verilog

    Here is my Verilog Code, I am tring to make a 32x32 sequential multiplier, 32 stages, here is one of the verision I have tried the other has the comblogic made out of always blocs and each odd stage is on negedge and the others are on posedge module mul_piped #(parameter word = 32, parameter...
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