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Recent content by Alice Lee

  1. A

    Adding parasitic Cap in pre-layout simulation

    thank u.
  2. A

    Adding parasitic Cap in pre-layout simulation

    Hi,everyone. I want to know do u adding some parasitic Caps in ur schematic when running per-layout simu? How to model these caps? I think they are mainly routing parasitic caps..... BTW, the process is tsmc28nm HPC thank u
  3. A

    Capacitively-coupled Chopper Instrumentation Amplifiers input impedance simulation

    thank you. i used pss+pac to check the voltage and current that can get a impedance. and i think pss+psp also can help
  4. A

    Capacitively-coupled Chopper Instrumentation Amplifiers input impedance simulation

    thanks a lot. i will work on PAC/PSS analysis.
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    Capacitively-coupled Chopper Instrumentation Amplifiers input impedance simulation

    Hi,all. I am studying the paper attached. i am wondering how to simulate the input impedance of CCIA in cadence. does anyone know?
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    the drive ability of the AFE

    Thanks for the advice. it's indeed important to care about the settling time of adc. and in my opinion, the peak current may be dominate. if the AFE driver can provide the average current that the ADC needs but can't provide the peak current, does it work? (i'm a junior designer and haven't...
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    the drive ability of the AFE

    Hi,all. I want to know how to decide the drive ability of the AFE in front of ADC. Actually, I'd like to understand it from the perspective of current that the ADC needs(e.g. dynamic switching current）instead of impedance. Is the largest current or average current dominate?
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    bootstrapped switch design

    Thanks a lot
  9. A

    bootstrapped switch design

    Hi, everyone. I tried to design a bootstrapped switch whose resolution is 13b. the sampling frequency is 100MHz, the input signal frequency is 1.27MHz. And i took this paper as reference. B. Razavi, "The Design of a Bootstrapped Sampling Circuit [The Analog Mind]," in IEEE Solid-State Circuits...
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