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Hello fellow chipdesigners :)
I am a PhD Student working at a circuit design department that normaly only does analog stuff. I learned all the digital workflow stuff myself with free resources online and till now everything has worked. You can imagine though that a lot of know-how is missing...
I have only worked with 2 technologies yet, but in both the deep n-wells were used isolate whole circuit blocks (at my current design even a square milimiter big block) from the substrate. For our optoelectronic designs the substrate will be biased to around -25V so any circuit needs to be...
Why could he share the deep n well for the three different positive voltages? Wouldn't each of the inverter contact the deep n-well with their own n-well? Or is this feature technology dependand?
For 2:
We are mainly working on optoelectronics, so any circuits has to be isolated from substrate anyhow (using a deep, low doped N-Well). Substrate level is around 25V lower than where the circuits operate. I know there is some coupling of substrate noise, so every block is enclosed with...
Thank you for that though, I haven't thought about that yet since we are doing research and our dies are glued to pcb's with a conductive glue and bonded straigth to the PCB.
TNS ist the total negative slack. Its the sum off the violating slacks on all paths. TNS=0 means you are good!
Max transition means that the clock transition is to slow on some paths (it violates the constraints you gave them). Have you built a clock tree yet?
@NotSam he wrote that he only uploaded the declaration of hi top module
You load all your verilog files, right? What I remember it is important to input the hirachy bottom up, eg.:
read_hdl -vhdl {FlipFlop.vhd counter.vhd wholeCPU.vhd}
Do you use a script to feed genus? if yes enter each...
Are you sure about the "clk"? I think it is only clk, without the " "
Also I would recommand that you dont call the SDC clock clk as the pin, so you allways know which signal you are working with!
My genus works without the "" but I havent tried with!
Hi guys!
I am currently working on a mixed signal project in research. I am at the beginning of my PhD and am working on an institute where a lot of analog knowhow is present. but only minimal digital. This is my topic.
While I am able to create digital design blocks in innovus, the know how how...
Thank you again! For the filler cells I calculated the leakage and it is definitly doable for my current design.
The only problem I have now is that I get DRC errors during LVS (not during DRC). It says unstable device fpr pdiode_DIODE_105. It has the error both at the diffusion area of the...
Thanks for that input!
At what point of the workflow do I add them? after CTS before doing routing with nanoroute?
Just as a side question: is there any reason to use regular filler cells over decap fillers?
Hi!
Today I encoutered a problem when porting a digital block design from innovus to virtuoso:
I extracted the netlist from Innovus with save netlist aswell as the DEF and imported them to virtuoso.
During LVS in virtuoso I discovered that all of the Flip-Flops with reset (the synthesis tool...
Hello fellow engineers!
I am looking for a guide on how to include a analog building block into innovus workflow.
I have a analog building block with around 200 signals going out. I need to connect all of them to my digital circuit.
Do I just synthesize the digital circuit as I am used to, then...
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