Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: Problem on post layout simulation
Just in case someone will run into similar trouble: the solution that worked for me was to include in your pex tech file the lvs rule file (which correspondingly defines all the layers) - just put "INCLUDE lvs_file_path" in the beginning of the pex file...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
