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I have followed the steps at from the Xilinx page up until the point that I had to run the GUI. I imported the said files, booted the Zynqboard with that data. However, the buttons "StartMasterPTP" and "StartSlavePTP" do not work.
Things I did not do:
I did not run the Linux kernel building...
Hello,
I have synthesised my Verilog HDL code in Synopsys DC and now I have to do a timing simulation. I do not want to use Xilinx or Altera tools as these will give me FPGA results. I want to know how to do the simulation taking into consideration my technology libraries (I suppose there has...
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