Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by alexhugo

  1. A

    Equivalent gate count of 100Kbits SRAM

    I actually found following useful document. **broken link removed** I found that each cell area is equivalent to half a gate (smallest NAND2) area. But you should consider also the overhead including the power lines, address/data mux, ....
  2. A

    Equivalent gate count of 100Kbits SRAM

    Hi, I have a design which has a 100Kbit SRAM. I have been able to synthesize my circuit with design compiler and I know the gate count (total area divided by smallest NAND2 area) of all circuit except the RAM. I don't have any memory compiler to find its actual size. I just need a rough estimate...
  3. A

    Why do I get too big library setup time?

    Problem is resolved. I was using a control signal to OR with rst and reset all flops. The number of flops in terms of 100's of thousands and I couldn't set it like RST to be ideal network.
  4. A

    How to create single bit odd parity generator?

    Your question is not very clear but if you have n bits of data and you want one bit which is parity of all n bits, you simply need to XOR all bits. Output of XOR is the parity of all n bits
  5. A

    Why do I get too big library setup time?

    This is the new report with more information. I don't understand how I can get rid of the library setup time. Helps are greatly appreciated.
  6. A

    Why does this net have such a big delay while it has only one fanout?

    I set some cells not to be used and the delay in the path is gone but the library setup time is still huge. This is new report with more information. I really don't know how the library setup time can be this big
  7. A

    Why do I get too big library setup time?

    Hi, I do a report_timing in dc_shell and I get a huge library setup time of -123.44ns You can see the last part of the timing report: Can you guess why a 40nm cell (FF) should have such a huge library setup time? clock period is 2.5ns Thanks Alex node_1/index_reg/D (SDFQND2BWP)...
  8. A

    Verilog for loop error.

    It should be iter=iter+1
  9. A

    Why does this net have such a big delay while it has only one fanout?

    Hi, In following timing report (generated by "report_timing -nets -capacitance -nworst 10"), output (ZN) of U65427 has 160.79ns delay. You can see this instance has one load (fanout). I need to find the reason for this big delay and resolve it. Also why library setup time is so huge? Design...
  10. A

    Why net (wire) delays are zero after synthesize?

    That might be true but wire_load_model is used for this purpose. What is the point of using wireloadmodels if synthesizer is going to assume zero delays for the nets?
  11. A

    Power Estimation or Analysis during RTL stage

    You must do a synthesis to be able to have an accurate estimate. This URL may help you: **broken link removed**
  12. A

    Wire_load_model in different levels of hierarchy

    Hi, I have few RTL codes (module A,B,C and D) instantiated in a top level module (TOP). TOP instantiates A, B, C and D and has also some glue logic. Size of A, B and C are between 25K to 50 K. TOP (A+B+C+D+GLUE logic) is about 200K. Which of the followings I should do? Should I do this: set...
  13. A

    What should be done if DRC (Design Rule Cost) is not zero after synthesizing with DC?

    Hi, What should we do next if we have none-zero DRC (Design Rule Cost) value after synthesizing with synopsys design compiler? I appreciate it if you could tell me what are all the steps and when we should say "OK this is good enough!" Thanks Alex
  14. A

    How can we meet timing ("SLACK MET") and none zero "DESIGN RULE COST" together?

    Re: How can we meet timing ("SLACK MET") and none zero "DESIGN RULE COST" together? I know how DRC works in analog design but I don't know where to start working on it and fixing it in digital circuit. Could you please help me and let me know where I should start and what I should do to fix the...
  15. A

    Need help to understand DC tcl commands

    Why don't you post the commands you need to understand so every one can help?
See more

Part and Inventory Search

Back
Top