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If the vref of circuit is very important .I think u can consider use BGR and voltage buffer to get the vref. This circuit has poor PSRR and temp coeffcient. If u have to use this circuit u can use 2 pmos or nmos in stead of cmos architecture. I think use a buffer behind it is a good choice. best...
Re: Comparator Desing paper
dear all
I'm considering to use this comparator in my sar_adc design. but my adc has reset mode which let comparator work in the unit gain closed loop with high capacitor load (about 60pf).My question is "Is the domain pole in this comparator in the output stage?"
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