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Alright!!! That was my problem. Started to look a lot of references and I saw Verilog examples that were using "reg mem[0:255]" and I supposed that I needed to do the same with my code. However, you have already clarified to me the idea of pseucode. Yes, the FSM I'm working on it, but I wanted...
Therefore, I don't need basically to write it in the Verilog. It is juts an abstract idea for understanding the counter and the sum itself? In other words, the pseucode represent the whole looping of the design.
Hello!
My name is Alex and I'm currently working on a datapath design. The instructions are: Design a system that sum the values stored in a memory from a specific address. The sum system includes the design of and finite state machine (FSM) and a datapath. A test bench is provided to validate...
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