Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Dear zhao,I had also meet this problem in my early design.At last,we find the root cause was because layout engineer did not put the DAC size value in LVS check.Do you want check it again.Other question, do you have self calibrating circuit in your 16bit sar adc design?I think design a 16bit...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
