Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Dear all, I am a (really2 green) newbie.
When I compare my synthesis result with paper reference, the area is almost same (0.1092 vs 0.0929 mm2*). However, the gates count is significantly different (25.65 KGE vs 16.79 KGE*).
*the latter result is my work.
Would somebody explain why this...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
