Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hai,
iam doing GLS for an soc...
i files i used are
1.post layout netlist 2.sdf 3.tfile
iam getting $width violations:these width violations are reported on the boundary isolation cells; for boundary isolation clock buffers are used
can any help me how to supress this width violations...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
