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Recent content by akp494

  1. A

    Info about negative setup and hold time

    Re: -ve setup and hold Hi -ve setip and hold times rae all with respect toa cell. Flip flops standalone as it is have only +ve setup and hold times. -ve setup and hold times come into play when Flip Flop is aprt of a cell. For example a scan flip flop. Scan flip flop consists of a Mux and...
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    Looking for UTMI+ specifications

    utmi specification Hi Chandramohan I do have UTMI specification. I am looking for UTMI+ which is basically designed for USB-OTG purpose. If you have UTMI+ spec please upload. It will be of great help to me. Thanx for your time Prasad
  3. A

    Looking for UTMI+ specifications

    If anyone has UTMI+ specification please upload it. This will be of great help to me. Many Thanks in advance
  4. A

    Mixed signal verification question with Nanosim + VCS

    Hello Blugate In your case I asume that the clock signal from Analog block is coming properly. But the moment it goes to digital domain you are seeing an unknown state for some time on the clock signal. So you may have to check the ADC(Analog to digital converter) models the tool is picking...
  5. A

    how to do postsimulation ?

    Hi Spauls Yes I mean gate level simulations. STA is a Static Timing check. Gate Level sims are dynamic timing checks along with the functionality
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    how to do postsimulation ?

    Hi mic_huhu Here is the way how you do it. I am assuming your testbench code is in verilog here. suppose your DUT top level is called rtl_top. module rtl_top(.....); ..... endmodule You might have synthesized the above module using Synopsys-DC. Now you will get a netlist corresponding to...
  7. A

    Why active low reset are used in Verilog?

    Re: Active low reset May be this paper on resets may be of some help .
  8. A

    Need to know the operation of FIFO in detail

    Re: FIFO May be you can check this paper as well
  9. A

    How to calculate the depth of FIFO?

    whatever whizkid said is true. but we can consider even more worst case. Lets say in the 200 clock cycles we receive data for 160 clocks continuously. Then we require a FIFO of depth 32 not 16. So the correct answer will be 32.
  10. A

    What is a shadow register and how is it used?

    Hello Can any please tell me what is a shadow register and what are the applications in which it can be used?? Any Verilog code or schematic will be very useful. Thanks akp
  11. A

    how to detect a pulse from a fast clock domain to a slow one

    Re: how to detect a pulse from a fast clock domain to a slow Toggle synchronizer
  12. A

    how to detect a pulse from a fast clock domain to a slow one

    Re: how to detect a pulse from a fast clock domain to a slow Use a Toggle synchronizer
  13. A

    Need information about VHDL-AMS

    This document might be of some help to you.
  14. A

    Mixed signal Verification

    Can someone please explain how verify digital/mixed signal designs . Simulation is never a problem. We can either use ASM Designer from cadence or Nanosim from Synopsys. Can we use the same test bench that have been used for digital block verification or do we need to develop a new test bench...
  15. A

    Mixed signal Verification

    Hi In my job I have been assigned the responsibility of verifying a analog-Mixed signal design. But I don't have any prior experience of analog design or mixed signal verification. I have been in the digital design front-end verification and design for the last 4 years. So I don't know where...
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