Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by akash singh

  1. A

    Spice simulation of Gate Level Netlist

    Can you point me to some tutorial.
  2. A

    Spice simulation of Gate Level Netlist

    I'm using UMC free libraries. Can you tell me which files to use as spice models and libraries for standard cells used in the netlist.
  3. A

    Spice simulation of Gate Level Netlist

    I have post synthesis netlist generated by design compiler. I want to perform spice analysis on this netlist. I don't know how to generate spice netlist and which tools to use. Can someone tell me how spice analysis is performed on the gate level netlist? Thanks in advance
  4. A

    Automating simulations in cadence virtuso

    @erikl Can I run the generated OCEAN scripts in some loop. If yes, is it possible to dump results like delay values to some text file?
  5. A

    Automating simulations in cadence virtuso

    Hi! I want to find out delay of a 16 bit adder designed in cadence virtuso icfb tool for a large number of input values and Vdd. I know how to simulate the design with a given input and find delays using delay function in waveform calculator. How can I do this analysis for a large number of...
  6. A

    [SOLVED] difference between set_max_transition and set_input_transition

    set_max_transition sets the maximum transition time, a design rule constraint, on specified clocks, ports, or designs whereas set_input_transition sets max/min transition time attributes on the corresponding input port.
  7. A

    How to generate block level constraints from top level constraints in synopsys DC

    Hi all! I have top level constraints for my design. I want to synthesize a particular block of my design for which I need to generate block level constraints using Top level constraints. I am using synopsys design compiler. I have heard about dc_allocate_budget command. Can someone provide...
  8. A

    Area vs operating frequency in ASIC synthesis

    Hi All, I am trying Synopsys dc tool for synthesizing my design. I tried different operating frequencies and observed the design area. Normally area should increase with increasing operating frequency but in my case design area for 220 MHz is somewhat greater than the area at 240 MHz. How is it...
See more

Part and Inventory Search

Back
Top