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Recent content by aka_rabbi

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    How does this OTA operate with very low voltages

    Hi. the attached picture is from the paper "K. Raczkowski, N. Markulic, B. Hershberg, J. Van Driessche and J. Craninckx, "A 9.2–12.7 GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter," 2014 IEEE Radio Frequency Integrated Circuits Symposium, Tampa, FL, 2014, pp. 89-92...
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    mosfet as a switch in 28nm technology

    thank you so much. Can you recommend a book that teaches layout from the EDA tool perspective(like how a designer would approach)?
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    mosfet as a switch in 28nm technology

    Hello, everyone. I want to know the proper way to use a single mosfet as a switch in the nano scale from anybody who has experience in design. I know that Vgs will turn the mosfet on or off. How do the L and W affect the device as a switch? what are the proper layout technique for switch? in...
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    layout extraction changing device

    I figured it out finally. somebody had changed the rule file. Thanks guys for your suggestions.
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    layout extraction changing device

    ok here is some background into my problem- the 1st pic is an LVS passed previous version(V2). 2nd pic is the layout spice for the resistor the 3rd pic is the failed LVS version(V5). 4th pic shows the unwanted 3rd terminal for the resistor $SUB=GND $[rjnwsti] --> what does it mean? What can i do...
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    layout extraction changing device

    when i run the LVS for my circuit, the layout extractor translates the resistor layout i placed- rnwsti(2 pin) as rjnwsti(3 pin). so i can't pass LVS. anybody have any tips on how to fix this? i am pretty sure source side of things are perfectly ok.
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    composite sync generation in ModelSim

    Hi. I have a very basic question. I have made the various signals required for composite sync signal generation[figure (1) with counters in modelsim. But how do i generate the composite signal from these as in figure(2)? I am totally confused because i don't know how these individual signals are...
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    question about PLL being in lock

    I am designing a type-2 PLL on cadence. Check the attached picture please. The vco output freq. is divided by two before going into the PD. I have two questions- 1. the control voltage never stabilizes. why? the loop is not really achieving lock, is it? 2. can i put the sinusoidal output of the...
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