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Recent content by aji_vlsi

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    A step-by-step Guide to SystemVerilog Interfaces - free Webi

    **broken link removed** Date : January 28, 2010 Time : 9.30 AM – 10:30 AM India Standard Time Date : January 28, 2010 Time : 3:00 pm - 4:00 pm Central European Time Date : January 28, 2010 Time : 9:00 am - 10:00 am Pacific Standard Time (USA) See: **broken link removed** or...
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    how ESL effects current functional verification methods?

    Re: ESL and Verification VMM/OVM both are moving to embrace ESL - via TLM connections to SystemC etc. See updates on the respective sites. BTW - ESL synthesis is still maturing and it is unlikely to take away RTL for atleast 5 years, so jobs are more and more on VMM/OVM for now.. Ajeetha, CVC...
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    Problem with code coverage ius82

    Re: Code coverage ius82 Try: nchelp ncelab COVSCNDRY My guess is you use svpp flow, but it is a wild guess. Look at irun flow or best is to ask CDN support Ajeetha, CVC www.cvcblr.com
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    Cadence Systemverilog Testbenches: bind program blocks

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    Help from knowledged ppl on choosing VLSI specialization.

    Re: Help from knowledged ppl on choosing VLSI specialization Hi Josh, If you are looking for a serious job oriented course consider looking at our EIC - it is not traditional training, rather "incubation" as we put you on to projects and provide various modules to achieve the same. You may...
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    Co simulation of SystemC files with VHDL testbench

    Dor, Look at their manual, I found: VHDL Instantiating SystemC We have Verilog/SV-SystemC training examples @ CVC, can quickly make it to VHDL if needed. Contact me offline info@cvcblr.com if interested. Good luck Ajeetha, CVC www.cvcblr.com
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    for ti interview - what topic i should concentrate

    Re: for ti interview Is it for VLSI? If so brush up Verilog/VHDL. If you have any higher level verification experience like E/SystemVerilog/PSL that will be a GREAT advantage. You may also consider our internship program at CVC: **broken link removed** and if you can fix up a topic for VLSI...
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    Any course on SystemVerilog

    iivdt Pradeep, We value your response, thanks! See my replies embedded: Yes that's typically meant for working professionals (what we call as Corporate customers). Yes indeed we offer that - we have 10-day course and also a 1-month course. This has been a good success so far with the...
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    FPGA final year project for electronic engineering

    fpga projects If you are genuinely interested in DOING it yourself and are looking for ideas & guidance contact us via www.cvcblr.com. If you are looking for pre-cooked ones with report etc. ready - don't even bother, we DO NOT provide it. Instead of paying that amount, go to www.opencores.org...
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    Documents for learning SystemC

    Re: Learning SystemC We (www.cvcblr.com) have a course on SystemC starting end of Sep 2009 if anyone is interested! Regards Ajeetha, CVC www.cvcblr.com
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    Where can we do a systemverilog OVM project

    ovm forum Hi Suyog, I believe you have spoken to my colleagues about this. CVC (www.cvcblr.com) has been pioneering this domain and have the right setup you are looking for. We have been doing successful 10-day, project based SV/VMM/OVM courses and are scheduling 2 for Sep 2009. For more...
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    Required : Book on Assertion

    Kindly send an email to: training <> cvcblr.com or cvc.training@gmail.com. Contact Jagadeesh @ 080-42134156, 9620209223 or Bagath via: 9916176014 for exact pricing details. For others, you may also want to read: Regards Ajeetha, CVC www.cvcblr.com
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    Post-synthesis gate-level VCS simulation (race condition)

    gate level synthesis Try turning on -debug or -debug_all for the SAKE of shutting down optimization and see if that helps. If yes, then we can further nail it down to specific code. Best is if it reproduced in a small testcase - the scenario you've described looks recretable, but does that...
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    Any course on SystemVerilog

    system verilog training in india Sorry to intervene on a customer-vendor related thread, but wanted to clarify few things. First of all YES, we at CVC offer some of the BEST courses needed by experienced folks in the industry (and have also extended the same to Freshers via 4 month...
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    Verilog code formatter

    verilog code Try verilog-mode.com - not as great as VHDL mode, but does a decent job. Ajeetha www.cvcblr.com
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