Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
yes your right!
At a time one clock source signal are present on lines but layout traces from other source will be act as stub to clock signal if i don't physically isolate trace form second source. for that purpose i am finding to trace isolation without affecting clock signal
FPGA I/O is working on 2.5V and I/O standard can LVTTL or LVCMOS. yes your right two jumper must be use as it is differential. But don't know what will be the effect of jumpers on clock signal. As only one clock source is present at time(clock signal will not present on traces but still traces...
I am designing Main board using Altera FPGA. In circuit I need external differential clock. On main board I have introduce one clock generator circuit also have provision to take clock from external daughter board. Clock frequency range is 10-200 MHz. There are two possibilities but at time one...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
