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Recent content by ajaychowdharykr

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    Fully differential OPAMP design for large input signal.

    Hi guys, I need to design a fully differential operational amplifier as an ADC driver. I will get +/- 0.5volt sinusoidal input signal and have to generate the differential signal with the DC shift(i.e 0.4-1.4 volt differential sinusoidal signal). The problem is that, if I can bias the input...
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    DAC design for 14- bit SAR ADC

    Thanks, @dick_freebird for the reply. I have one more query, initially, I was calculating DNL and INL as: 1. Applying ramp input and had taken 2^N samples for N-bit. 2. Giving the sampled input to the ADC and obtained Digital output corresponding to each input. 3. Calculating the equivalent...
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    DAC design for 14- bit SAR ADC

    Thanks, dick_freebird for the reply. I have already modeled as u said, in MATLAB. But now I wanted to do the same in Cadence. I wanted to write the monte carlo model file by adding an additional variable to the nominal value of the capacitor. This variable must follow Gaussian distribution so...
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    DAC design for 14- bit SAR ADC

    Hi All, I am designing Split DAC for 14-bit SAR ADC. I wanted to analyze the effect of Mismatch and process variation of the capacitor on the overall SAR ADC. For that, I wanted to run a Monte Carlo simulation on the DAC unit and I am using UMC 180nm Technology. However, I am not getting the...
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