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Recent content by airboss

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    Can I use different kinds of MOSFETs in one circuit (.18 CMOS process)?

    Re: .18 cmos question just a quick glance of this thread. i guess to convince yourself, you should run simulation and check if any of the devices are breakdown.
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    Relationship between Vdssat and Vov

    vov vgs i've forgot the formal answer to this question but i know if you wanna receive a complete answer to this, please read the text book "operation and modelling of mos transistor" by Y. Tsividus. if you just need a 1-st order evaluation, then worry only about vov. if you're running...
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    two questions about pipelined adc

    1\ what other topologies do you wanna compare with? also, what are you concerned about, the speed, power consumption or something else? 2\ you need to understand your other requirements, such as your GBW, your noise limitation, settling speed, and etc. it's hard to give you any input just based...
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    How to set the common mode feedback loop ?

    simply speaking, you need to create an output CM voltage detector. the detected output CM voltage then needs to go to a "comparator" because you want to know "is it pretty close to the desired CM voltage or not." then, you need to make a negative feedback loop so that when the output CM voltage...
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    request potential interviews questions on SAR ADC

    I'm currently looking for a job in the analog and/or mixed-signal IC design right now. I was assigned mainly to the digital core when I was working on the SAR ADC. I do put it on my resume but most of the people questions me on the analog core. So can people throw out some potential questions? I...
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    please advise reference on ....

    Hi, I was running simulation over a boost generator but I didn't fully understand how it worked. As I understand I can look up the topic of level shifter, charge pump and voltage doubler. Please advise any textbook or slides I can find useful info.
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    questions on ON Resistance

    Hi, I have a few questions about ON resistance. 1) "MOSFET can serve as a switch; it can be on when it carries zero current." This statement somehow doesn't make sense to me. Ron is the equivalent resistance across D and S so if I_DS is zero, doesn't it mean infinite resistance, or an open...
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    question on frequency compensation for 2-stage OTA

    stage ota Hi, A question regarding the frequency compensation for a 2-stage OTA. In Razavi's textbook, he assumed the dominant pole & the 1st non-dominant pole before compensation are the O/P pole of the 1st stage & the 2nd stage, respectively. He explained that to acquire each pole's location...
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    need bandgap questions for interview

    can somebody show me the answers? i still have no clues after one more glance at razavi's and allen's.
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    need bandgap questions for interview

    Hi, I have an entry-level job interview coming up soon. One of the subjects they will ask me is on bandgap reference. I do not have any design experience but book knowledge. I wonder how they would ask questions about it. So can anybody throw out some threads? Thanks! -airboss
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    questin in fully op amp ?

    Hi, just few thoughts up in my head. 1) test each stage separately. say, only work on your 2nd stage and see if increasing the current in your bias ckt changes anything in your main ckt. 2) i think it's a little hard to help you w/o your schematic. can you upload ur schematic? cheers
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    questions about OP design procedure in TSMC018 technology

    Hi, i'm given a spec and i have to achieve the gain, in TSMC018. after giving current and allocating the overdrive voltage, i did the simulation. i extracted gm and ro for each transistor, and plug the numbers into the gain equation to calculate the gain. however, the order of the magnitude of...
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    questions about pipeline adc mechanism

    Hi, i've seen this block diagram for pipelined adc in many places but i'm really confused. please help me to understand this. we know this will be implemented by S/H capacitor circuit. 1)we see a 2X here. i guess this is because of capacitor charging transferring from sample phase to holding...
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    questions about pipeline ADC design

    Hi, We're working on a pipeline ADC design and we need some help here. Our question is on the spec of the op. We're asked to get settling correct within 1/4 LSB when we input a sine wave of frequency Fs/2 of full-scale amplitude. 1) we did ask our professor what that means but we didn't really...
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    Question: amplifying signal by current mirror

    Hi, i have a question regarding using current mirrors to process signals. this is something razavi mentioned in his textbook. given a reference mos ckt with ideal current source Iref and (W/L)ref. the other mos ckt mirroring current from reference ckt is Ix and (W/L)x. so razavi says that if...

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