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Recent content by airace

  1. A

    What's the MOS function added between 1st and 2nd stage ?

    Re: about the mos'S effect compensation??
  2. A

    Idrive spread measurement

    ....No!..Have set it to 50u...this was a sample schamtic i made for the post
  3. A

    Idrive spread measurement

    ..also forgot to mention that, I am measuring cirrent thro' dummy voltage source...to find Idrive. Regards, @ir@ce
  4. A

    Idrive spread measurement

    Hi, I am trying to measure Idrive process spread for PMOS/NMOS (TSMC 0.18um). The test setup i have used is below :- The NMOS size i used is actually 50/0.18..and simulation is with specter with conditions being Vgs =1.8 and Idrive to be measured at Vds = 1.8 v Problem : Id is reaching...
  5. A

    Difference between Vih(ac) & Vih(dc)

    Can anyone tell me the difference between these 2 parameters. This is normally specified for I/O buffers. I am attaching a memory datasheet which uses these specs Thanks in adv
  6. A

    channel length modulation

    ....also, I did try the method given in Hollberg Appendix.. which uses the y=mx + b method.....I could not figure out how is measuring 'b'.... ........if someone has done this...can you please throw some light on it? Thanks in adv @ir@ce
  7. A

    Help me understand the calculation of W/L ratio in analog

    Re: Need help. Srivats.. ...please remember following 2 rules for current mirrors.. 1. always use Channel length which is 4-5 * Lmin ...(though this is ideal for DSM i.e < 0.25u)....the best thing wud be for u to characterize the MOS and see for which 'L' Id slope is less...use that length 2...
  8. A

    channel length modulation

    Hi experts... I am trying to characterize a MOS for it's design parameter.. Can you tell me How I can measure 'lambda' using analog artist? Regards, @ir@ce
  9. A

    CMOS OP-Amp - Where is the noise limit?

    ...also remember, PMOS diff pair will give better noise performance... Regards, @ir@ce
  10. A

    capacitor using CMOS transistors ?

    Hey, I guess the illustration is all screwed up....well one terminal is the gate....and connect drain & source to bulk connected to VSS forms the other terminal (ofcourse - u now have a problem, a capacitance is formed only between a node a ground) Regards,
  11. A

    capacitor using CMOS transistors ?

    Normally, if a process is a dual poly process one goes in for dual poly caps. But most processes are single poly processes. It is a common practise to use the MOS cap a capacitor | G -------- D----| | |----S |------|-------| VSS Hope the...
  12. A

    What is the function of the circuit in the picture?

    This is nothing but an invertor and is common in I/O circuit design. Primarily used for situations where the X'tors are LV devices and you want to operate of higher power supply. This is primarily to handle VDSmax violations. Regards,
  13. A

    How to convert extracted view to schematic in IC5?

    converting parasitic netlist to schematic Some companies have a methodology of "production schematic" & "design schematic". The first actually accounts for parasitics and is used before the lay-out is done by rough estimation of parasitics. If u want to do this, IC5 gives u a option. 'Q' on a...
  14. A

    Calculating Capacitance

    calculating gate capacitance Well, here is a idea i can give u, w.k.t i = c* dv/dt , apply a unit ramp i/p to gate of MOS, and measure current, it will be equal to the cap in magnitude. rgds,
  15. A

    tsmc_.18 proce$$ description

    here it is...zip file contains lib-spec and users guide (this is all we got with the PDK).... thx,
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