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Recent content by aifi

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    How to Choose a Voltage Reference

    Hi all.. Just for curious, why the voltage references are always set to 1.25V,2.048V,2.5V,3V, and so on..could anyone tell me please. thanks
  2. A

    Voltage reference for adc

    Thanks all.. i have attached the simulation result of the voltage reference. Erikl, i still dont understand how did you estimate +-1/4 changes from 0.27mV variation. could you please explain me base on the attached simulation result? Thanks
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    Voltage reference for adc

    Hi all.. i need your help regarding on this: i have designed a voltage reference with 1.3ppm/C over the temperature from -50 to 125. the voltage reference at typical condition is about 1.183V. could anyone tell me how to determine the exact resolution bit for ADC that compatible with the...
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    Opamp design in bandgap reference(BGR)

    thanks all.. how much noise should we consider for example if the noise going into differential input of amplifier?,if the gain of the amplifier is very high, then the input range of the amplifier is small, distortion will occur at the output voltage if the noise causing the input voltage...
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    Opamp design in bandgap reference(BGR)

    Hi all.. what should we really consider in designing opamp in BGR? thanks
  6. A

    Skin effect at high frequency.

    thanks dick_freebird , now i got cristal clear about the issue...
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    Skin effect at high frequency.

    Hi all.. i still wonder whether the EDA tools can deal with skin effect when performing the post layout simulation..can everybody advice me..thanks
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    interface ADE with Hspice

    hi all.. just a question, how write a script in order to interface hspice with ADE? i was quite wonder because everytime i choosed hspice in ADE to run simulation, error occurs as can be seen in CIW. Kindly advise me regarding this matter thanks :?:
  9. A

    interface hspice with ADE

    hi all.. just a question, how write a script in order to interface hspice with ADE? i was quite wonder because everytime i choosed hspice in ADE to run simulation, error occurs as can be seen in CIW. Kindly advise me regarding this matter thanks
  10. A

    extraction using calibre

    hi all.. when we do extraction using calibre, then the tool will create .sdef file for us, just for curios whether the tool extract all paracitics element through the transistor level or it just extract paracitics for interconnection only? as i know, the standard cells already have the timing...
  11. A

    convert verilog to spice file to perform LVS(calibre)

    calibre, verilog lvs hi all... to perform LVS using calibre, we need spice file as our source and compare with the layout. i heard that we have to exclude the dummy pads in our design before doing LVS,is it true? if yes, how to exclude that pads if i used Encounter(cadence) as my APR tool. thanks
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    How to generate .alf file from .db file?

    Re: .alf file when people want to perform synthesis using buildgates,they need .alf file, lets say that we dont have that file and only have .db file (synopsys),so how to convert .db file to .alf file?
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    How to generate .alf file from .db file?

    hi all.. if we have .db file,then how to generate .alf file? any tools to generate .alf file?
  14. A

    How to do LVS in Virtuoso only with layout?

    hi all... i still wonder how to do LVS if we only have layout ? how to generate schematic from the layout?
  15. A

    What's the purpose of DFT (design for test)?

    hi all.. why test? why add test logic?
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