Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
then u have two cases,
case1: for a pmos to turn on, Vds≤(Vgs-Vt)
Vd≤(Vg-Vt)
Vd< 12 - 0.4
Vd< 11.6
so for a 0.18µ tech...Vd< 11.6 volts ,
other wise the probable cause is the noise margin, u have to make the sizing such that it is...
Re: Need help in SRAM design
check your bit line and word line...
first, when you do the writing make both the bit line are compliment of each other.
next select your bit line both high to load the data
in both these cases the word line should be high..
finally in the last stage u will get...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
