Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: Verilog-A questions, plz continue help in this thread
Well, Thanks for helpful replies...
I have some other questions...
1. What is the @cross() function can do in digital block such as a flip-flop? does it have other similar functions? what are them? how to add a tolerance in both time...
verilog-a initial keyword
Hi all,
This is my first time to expose to Verilog-A, anyone help me please by answering these simple questions (hopefully)
1) What is the mean of "descipline" and "nature" statements? where do I use?
2) What is it meant by the backquot character: (`) when it come...
Okay, i know that i should use just shift register,
but i forgot to say that it should satisfy two things:
1. work in bidirectional, i.e. serial <=>parallel
2. work for high frequencies up to 100MHz
Thanks,
Sawaf,
Hello,
I want to get models for simulation and PCB layout of ADC, how can i get them, and what is the best tool you suggest to simulate? (Rem. They're Discrete component i.e. ADC ready IC, i'm not an IC designer)...
Thanks in advance,
Ahmad,
Dear all,
I am looking for a schematic and pcb layout as well as circuit explaination if available (layout is not critical) for an FM Tx and/or FM Rx in one or more of the following bands:
1) Broadcast FM band
2) ISM band
3) GSM Band (Up or down links)
If someone can kindly give me such...
Re: @DS with Verilog
Yes, please anybody tell how to add Verilog-A blocks in ads...
I'm sure that someone will do, and waiting for help from you
Thank you for help,
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
