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Recent content by Aggieland

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    Time Varying AWGN Channel Model

    In His Name Dear All I have a problem. I have a Simulink model for MIMO System which I add AWGN noise at the end. I am looking for a "time varying AWGN Channel". And I don't know how to model this to make it reasonable. Basically we need to change the SNR of the channel butwe need this changes...
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    Synopsys Design Compiler QUESTION

    In His Name HI I am trying to retime my pipelined data path. My problem is after retiming I need the power consumption of each pipeline stage separately. Is there any way that I can find the power consumption of each stage automatically? We came with this Idea. We can Apply the clock gating to...
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    Synopsys Design Compiler

    We came with this Idea. We can Apply the clock gating to our registers and after retiming (or may be before retiming) we can disable all the registers of all stages but one stage. In this way the power consumption of all registers of the stages and combinational logic after that will be zero do...
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    Synopsys Design Compiler

    We have the top level simulator that tells us exactly when a stage is clock gated and we are trying to calculate the power using design compiler. We have the RTL code for our design. I know that using .vcd the power estimation will be more accurate but we try to calculate power of each pipeline...
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    Synopsys Design Compiler

    It was helpful. Thanks
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    Synopsys Design Compiler

    But How can I measure the power consumption of each pipeline stage?
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    Synopsys Design Compiler

    The problem is I used clock gating and I may disable one stage while there is no data for it. So, in that case the power consumption will be less. I need to know the power of each pipeline stage to calculate the power saved with clock gating
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    Synopsys Design Compiler

    In His Name HI I am trying to retime my pipelined data path. My problem is after retiming I need the power consumption of each pipeline stage separately. Is there any way that I can find the power consumption of each stage automatically? Please Help me. Regards;
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    Design Compiler

    In His Name Hello everybody I am new in ASIC Design and I have a problem. I am trying to do pipeline retiming for my verilog code using design compiler. The problem is I need to know the power usage of each stage of pipeline separately. Can anybody help me? Please, Please Help me...

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