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Recent content by afz23

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    Remote programming ,read back and default program setting

    Thanks Barry I have time constraint to implement this,it would be great help if you can give some reference of similar application or at least explain with block schematic for both microcontroller and latch based approaches.
  2. A

    Remote programming ,read back and default program setting

    Hi, I have a task to remotely program frequency selection bits of a RF transmitter. The transmitter provides a 16 bit selection pins interface.I accomplished this task by making a serial to parallel bit converter circuit using some general purpose digital ICs . I send a 16 bit frequency select...
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    Delay between +VCC and -VEE supplies of opamp

    Thanks Klaus for your comments. Can you please suggest a comparator IC ,which can handle upto 10Mbps data rate?
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    Delay between +VCC and -VEE supplies of opamp

    It's a single ended output, which is driving IF port of mixer. Its mixer as a BPSK modulator, which receives carrier at LO port and gives modulated output at RF port. - - - Updated - - - I am using AD8001 as comparator.
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    Delay between +VCC and -VEE supplies of opamp

    I am using power supplies which have time delay of 20ms between +VCC and -VEE to power an Opamp 8001.It is a level shifter circuit. It is used for converting a TTL signal to bi-polar signal at 3Mbps. Is there any issue if opamp gets delayed supply and opamp o/p drives a diode based double...
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    Need to program a synthesiser IC using microcontroller

    Hi Klaus, I will be sending a command via a wireless or RF link, The command will be received by a command decoder and send the frequency selection bits ,clock and enable signal toward the synthesizer IC.
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    Need to program a synthesiser IC using microcontroller

    I am looking to program a 21 bit fractinal N frequency chip PE9763 manufactured by Peregrine semiconductors ,using a micro controller, The chip has R,M,A and K registers to be programmed to generate an exact frequency locked to the reference source. Kindly suggest me the simplest micro...
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    BPSK at MW frequency

    The mixer approach is similar to the first method shown by you in the block scheme,what do you suggest in place of a mixer for 0 and 180 degree phase modulator. what are the constraints for high bit rate BPSK? Whether it's important,that carrier and data to be synchronised wrt same clock,or...
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    BPSK at MW frequency

    Thanks biff44 I plan to use a mixer to generate bpsk signal. I am mixing data stream with MW signal to do the job.
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    BPSK at MW frequency

    I have a data stream @3Mbps, I want to modulate my carrier at 4GHz using BPSK scheme. Kindly suggest,the right approach for doing this and references for such a high frequency digital modulation. Just wanted to add that,the data is a CDMA code,which needed to be transmitted using a MW link.
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    Protection against reverse leakage in commercial Equipment

    I use Keysight(earlier Agilent) signal source (E8257D PSG analog) for testing my circuits. Though it also uses PLL circuit to synthesize the frequencies,but it is not affected by problems like oscillator load pulling problems etc. What's the order of reverse isolation(in dB) provided by the...
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    How to calculate ISOLATION VALUE for VCO output?

    The modulator/mixer should not be operating at same or integer multiple of locked VCO frequency to avoid VCO frequency pulling. If modulation is to be done at 1500MHz, lock VCO at 1000MHz ,divide it by 2 makes it 500MHz and then multiply by 3 ,to make it 1500MHz. So,by doing so VCO and...
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    How to calculate ISOLATION VALUE for VCO output?

    This post was by mistake posted in wrong forum,I am re-posting it here: I have found out experimentally,I need an isolation of better than 80dB between VCO and mixer/modulator to avoid VCO frequency pulling to a great extent. Is there a simple mathematical equation to find out before hand...
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    Why PLDRO can be designed only by SPLD method?

    What I understand from the literature survey,is that a desired frequency is injected in DRO,to make it resonate and oscillate at the frequency,called "injection locking". But,otherwise,VCOs are made to oscillate at the desired frequency by sweeping control voltage,when VCO and reference signal...
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    Why PLDRO can be designed only by SPLD method?

    I am looking for a design to implement Phase locked DRO or PLDRO. During literature survey, I find the only way to implement this is by using a SRD comb generator and a phase detector to phase lock the Vt-DRO,it requires a sweep circuit too(sampling phase locked detector,SPLD),which makes it...

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