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Hi everyone,
Has anyone had experience with TSMC 180 layout extraction?
I am trying to run a mismatch/process monte-carlo simulation, using TSMC180 design kit for my extractec_view from layout. The problem is when I run the simulation on adexl only process variation works and the mismatch does...
Hi guys,
I was checking LVS check in the circuit below.
Then shows up this message saying that PWBLK has StampErrorFloat
Does anyone have already this problem and knows how to solve this? I tried to put some nWell and pActive vias, but it didn't work.
This is how my LVScheck is set.
Hi, I'm trying to simulate my circuit, using the resistor RSND_MML130E from the UMC130 libraries, but when I start simulating I get the following message:
Elaborating the design hierarchy:
ncelab: *N,SFEDPL: Deploying new SFE in analog engine.
ncelab: *W,CUNOUN: Cannot find any unit under...
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